1. Technical Field
The present invention relates to a contact for contacting an impurity region formed in a semiconductor substrate and to a method of forming the contact.
2. Description of Related Art
Recently, as the capacity of semiconductor memory devices such as DRAMs has increased, various arrangements have been proposed to increase the integration density of such memory devices. A one-transistor/one-capacitor memory cell is particularly well-suited for highly integrated memory devices since each memory cell is constituted by a small number of elements. Various types of one transistor/one capacitor DRAM cells are known, e.g., planar-type, stacked-type, and trench-type.
A trench-type memory cell is provided by forming a deep trench in a silicon substrate. A capacitor is then formed in the trench. Using such an arrangement, the cell area can be made smaller and the integration density can be greater as compared to a planar-type memory cell. In addition, discontinuities in wiring layers can result at step portions as the size of planar-type and stacked-type memory cells is decreased. In contrast, since the plate electrode of a trench-type capacitor is buried in the semiconductor substrate, the surface of the substrate is relatively planar and the wiring layers may be more accurately patterned. According to a conventional method of manufacturing a trench-type memory cell, an impurity such as arsenic or phosphorus is diffused from a bottom portion of the trench such that the diffusions from adjacent trenches are connected to form a buried plate electrode. The buried plate electrode functions as a wiring to which a potential may be applied. However, since this wiring layer is buried in the semiconductor substrate, it is difficult to apply a potential thereto.
One solution to the problem is to provide a "terminal trench" as described in U.S. Pat. No. 4,918,502. In this arrangement, the oxide film in one of the trenches is removed by photolithography and an N-type diffusion region is outdiffused from the side wall and bottom wall of this trench. This N-type diffusion region contacts the N-type diffusion regions outdiffused from the other trenches. A potential may then be applied to the wiring layer via the N-type diffusion region surrounding the terminal trench.
However, this and other arrangements for applying a potential to the buried plate generally require additional processing steps such as additional photolithography steps. This complicates overall fabrication process. Accordingly, there is a need for a contacting a buried plate or other deep diffusion region which does not require complex processing.